In the design of a particular circuit, the design engineer typically identifies a set of illegal vector sequences that, if applied to the corresponding input or inputs of the circuit in the corresponding sequence of one or more cycles, can trigger spurious or unpredictable circuit behavior. As part of the verification process, a symbolic simulator often is employed to generate a separate set of illegal vector sequences. The set of illegal vector sequences generated by the design engineer and the set of illegal vector sequences generated by the symbolic simulator then can be compared to ensure that there was not an error in either or both of the design engineer's analysis or the operation of the symbolic simulator. As part of this analysis, the relationship between the two sets is determined (i.e., whether the sets are equal, whether one set is inclusive of the other, or whether one or both sets include illegal vector sequences not found in the other set). This relationship then can be interpreted to verify the correct analysis of the design engineer and the correct operation of the symbolic simulator.
In many instances, the sets can include thousands, tens of thousands, or even millions of illegal vector sequences, thereby making a direct comparison of the two sets to determine their relationship memory-intensive and computationally difficult, thereby preventing the design engineer from efficiently evaluating the circuit designed. An improved technique for verifying the relationship between sets of illegal vector sequences therefore would be advantageous.